Explanation of the Tau Scaling Law (韬定律 / τ Scaling Law) by Doubao app

Explanation of the Tau Scaling Law (韬定律 / τ Scaling Law) by Doubao app 

 

1. Basic Background & Origin

 

Proposed officially by Huawei at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) on 25 May 2026, delivered by He Tingbo, head of Huawei’s semiconductor business .

It is an original industry evolution principle for post-Moore’s Law era, designed to break the bottlenecks of traditional semiconductor development guided by Moore’s Law for over 60 years .

 

In circuit science, τ (tau) stands for time constant, mainly referring to RC delay—the total time a signal takes to switch states and travel through devices, circuits and wiring paths . The smaller τ is, the faster and more energy-efficient the whole system operates.

 

2. Core Concept: Shift from Geometric Scaling to Time Scaling

 

- Moore’s Law traditional logic: Improve chip performance mainly via geometric scaling—continuously shrinking the physical size of transistors, fitting more components into the same chip area.

This route now hits severe physical limits (atomic-level constraints) and skyrocketing manufacturing costs for advanced process nodes, with diminishing performance returns .

- Tau Scaling Law core logic: Take time scaling (minimizing τ) as the primary optimization target, instead of only pursuing smaller transistor sizes.

Its fundamental principle: systematically reduce the overall time constant τ across devices, circuits, chips and full electronic systems, to lift computing speed, energy efficiency and equivalent transistor density without over-reliance on ultra-advanced lithography processes.

 

Analogy:

Moore’s Law = make workers (transistors) smaller to fit more in a factory floor.

Tau Scaling Law = redesign factory routes & workflows to shorten traveling distance for signals, letting data circulate faster even with unchanged floor space .

 

3. Core Enabling Technology: LogicFolding

 

The landmark technology to implement Tau Scaling is LogicFolding (逻辑折叠) :

Break the traditional 2D flat layout of chips, restructure and stack logic modules vertically. It drastically shortens critical interconnect wiring paths, cuts signal transmission delay, raises transistor density and energy efficiency within the same manufacturing process.

Huawei’s upcoming Kirin chips launching in autumn 2026 will be the first mass-produced chips adopting LogicFolding architecture .

 

4. Four-Layer Systematic Optimization System

 

Tau scaling optimizes τ throughout the full industrial chain:

 

1. Device layer: Shorten transistor switching delay;

2. Circuit layer: Apply LogicFolding to compress wiring latency;

3. Chip layer: Optimize internal data scheduling and inter-chip interconnection;

4. System layer: Software-hardware co-design to reduce overall idle & waiting time of the whole electronic system .

 

5. Practical Verification & Outlook

 

Huawei has verified the Tau principle via 381 mass-produced chips over six years, covering smartphones, AI computing, automotive and infrastructure sectors .

According to Huawei’s roadmap, chips built on Tau Scaling Law can reach transistor density equivalent to a 1.4nm-class process by 2031, achieved by architectural & system optimization rather than relying solely on top-tier manufacturing nodes.

 

6. Significance

 

It offers a sustainable new development paradigm for the global semiconductor industry beyond Moore’s Law, diversifying technological paths for chip performance upgrade amid physical and economic limitations of traditional geometric scaling.